Increasing processing speeds of devices such as graphics processors, hard disks, network cards, and other high speed I/O devices have created a need for an increased bandwidth for communicating between devices. One way to increase bandwidth between the bridge circuit and the I/O device is to use a differential communication link such as PCI Express™, HyperTransport™, SATA, USB, and other suitable differential communication links. Such interfaces are a flexible, hybrid serial-parallel interface format that uses multiple differential communication links often referred to as lanes. Each link includes transmit lanes to transmit information and receive lanes to receive information.
In high speed transmission, there are losses in the lanes. In order to compensate for the losses, transmission circuits associated with the transmit lanes use de-emphasis to reduce the transmitter data amplitude for repeating bits of data. More specifically, data is transmitted at full amplitude for each polarity (or state) transition (e.g., 0 to 1, 1 to 0, 1 to −1, −1 to 1, etc.) and thereafter repeating bits of the same polarity (or state) are transmitted at reduced amplitude.
Referring to FIG. 1, a typical prior art transmission circuit 100 includes a predriver circuit 102 and a de-emphasis circuit 104. The transmission circuit 100 can include a current mode driver circuit (not shown) or a voltage mode driver circuit 106. In some applications, voltage mode driver circuits are preferred over current mode driver circuits because they consume less power when transmitting at full power (e.g., not de-emphasizing repeating bits). The de-emphasis circuit 104 provides a differential voltage transmission signal 108 via a first terminal 110 and second terminal 112.
The de-emphasis circuit 104 includes a first uni-directional current source 114, a second uni-directional current source 116, a third uni-directional current source 118, and a fourth uni-directional current source 120. The first uni-directional current source 114 is coupled between a first power source 122 and the first terminal 110. The second uni-directional current source 116 is coupled between the second terminal 112 and a second power source 124, which provides a supply voltage less than the first power source 122. The third uni-directional current source 118 is coupled between the first power source 122 and the second terminal 112. The fourth uni-directional current source 120 is coupled between the first terminal 110 and the second terminal 112.
In general, the voltage mode de-emphasis circuit 104 de-emphasizes the differential voltage transmission signal 108 (e.g., reduces transmission amplitude) by using separate uni-directional current sources to source current from a positive terminal and to sink current into a negative terminal. For example, if the differential voltage transmission signal 108 has a negative voltage on the first terminal 110 and a positive voltage on terminal 112, current source 114 sinks current into terminal 110 while current source 116 sources current from terminal 112. Likewise, if the differential voltage transmission signal 108 has a positive voltage on the first terminal 110 and a negative voltage on terminal 112, current source 118 sinks current into terminal 112 while current source 120 sources current from terminal 110.
A control circuit 126 selectively controls the current source pairs 114, 116 and 118, 120 based on polarity (or state) signals 130, 132 from predriver circuit 102 in order to de-emphasize the differential signal 128. The polarity (or state) signals 130, 132 are based on the polarity (or state) of the differential signal 128. More specifically, the control circuit 126 determines whether a polarity (or state) change of the differential signal 128 has occurred. If the polarity (or state) change has not occurred, the control circuit 126 enables the current source pairs 114, 116 and/or 118, 120 in order to de-emphasize repeated bits of data of the differential voltage transmission signal 108. For example, if a voltage at terminal 110 is greater than a voltage at terminal 112, the control circuit 126 enables uni-directional current source 120 to source current from terminal 110 and enables uni-directional current source 118 to sink current into terminal 112. If, for example, a voltage at terminal 110 is less than a voltage at terminal 112, the control circuit 126 enables uni-directional current source 114 to sink current into terminal 110 and enables uni-directional current source 116 to source current from terminal 112
Accordingly, the more bits that are repeated and thus de-emphasized, the more current the uni-directional current sources 114, 116, 118, 120 provide, which in turn increases power consumption of the de-emphasis circuit 104. For example, in one embodiment, an extra 9 mA of current is required in order to achieve 6 dB of de-emphasis. As such, more power is consumed by the de-emphasis circuit 104 when using the extra 9 mA to de-emphasis the differential voltage transmission signal 108.
It is therefore desirable, among other things, to provide a de-emphasis circuit for a voltage mode driver that consumes less power than conventional de-emphasis circuits.